Nonvolatile memory circuits such as electrically erasable programmable read only memories (EEPROM) and Flash EEPROMs have been widely used for several decades in various circuit applications including computer memory, automotive applications, and video games. Many new applications, however, require the access time and packing density of previous generation nonvolatile memories in addition to low power consumption for battery powered circuits. One nonvolatile memory technology that is particularly attractive for these low power applications is the ferroelectric memory cell. A major advantage of these ferroelectric memory cells is that they require approximately three orders of magnitude less energy for write operations than previous generation floating gate memories. Furthermore, they do not require high voltage power supplies for programming and erasing charge stored on a floating gate. Thus, circuit complexity is reduced and reliability increased.
The term ferroelectric is something of a misnomer, since present ferroelectric capacitors contain no ferrous material. Typical ferroelectric capacitors include a dielectric of ferroelectric material formed between two closely-spaced conducting plates. One well-established family of ferroelectric materials known as perovskites has a general formula ABO3. This family includes Lead Zirconate Titanate (PZT) having a formula Pb(ZrxTi1-x)O3. This material is a dielectric with a desirable characteristic that a suitable electric field will displace a central atom of the lattice. This displaced central atom, either Titanium or Zirconium, remains displaced after the electric field is removed, thereby storing a net charge. Another family of ferroelectric materials is Strontium Bismuth Titanate (SBT) having a formula SbBi2Ta2O9. SBT has several advantages over PZT. However, both ferroelectric materials suffer from imprint and fatigue. Imprint is a tendency to prefer one state over another if the ferroelectric capacitor remains in that state for a long time. Fatigue is characterized by a gradual decrease in net stored charge with repeated cycling of a ferroelectric capacitor. Fatigue, therefore, is directly related to the number of memory accesses of a ferroelectric memory cell. Moreover, fatigue may be significantly greater for reference or dummy cells in the ferroelectric memory. These reference or dummy cells are accessed every time a memory cell on their respective column is accessed to produce a reference voltage on a reference bit line for comparison with a data bit line. Thus, fatigue for a reference or dummy cell may be two orders of magnitude greater than for a normal memory cell.
A typical one-transistor, one-capacitor (1T1C) ferroelectric memory cell of the prior art is illustrated at FIG. 1. The ferroelectric memory cell is similar to a 1T1C dynamic random access memory (DRAM) cell except for ferroelectric capacitor 100. The ferroelectric capacitor 100 is connected between plateline 110 and storage node 112. Access transistor 102 has a current path connected between bitline 108 and storage node 112. A control gate of access transistor 102 is connected to wordline 106 to control reading and writing of data to the ferroelectric memory cell. This data is stored as a polarized charge corresponding to cell voltage VCAP. Capacitance of bitline BL is represented by capacitor CBL 104.
Referring to FIG. 2, there is a hysteresis curve corresponding to the ferroelectric capacitor 100. The hysteresis curve includes net charge Q or polarization along the vertical axis and applied voltage along the horizontal axis. By convention, the polarity of the ferroelectric capacitor voltage is defined as shown in FIG. 1. A stored “0”, therefore, is characterized by a positive voltage at the plateline terminal with respect to the access transistor terminal. A stored “1” is characterized by a negative voltage at the plateline terminal with respect to the access transistor terminal. A “0” is stored in a write operation by applying a voltage Vmax across the ferroelectric capacitor. This stores a saturation charge Qs in the ferroelectric capacitor. The ferroelectric capacitor, however, includes a linear component in parallel with a switching component. When the electric field is removed, therefore, the linear component discharges and only the residual chargeQr remains in the switching component. The stored “0” is rewritten as a “1” by reversing the polarity of Vmax across the ferroelectric capacitor. This charges the linear and switching components of the ferroelectric capacitor to a saturation charge of −Qs. The stored charge reverts to −Qr when the voltage across the ferroelectric capacitor is removed. Finally, coercive points Vc and −Vc are minimum voltages on the hysteresis curve that will degrade a stored data state. For example, application of Vc across a ferroelectric capacitor will degrade a stored “1” even though it is not sufficient to store a “0”. Thus, it is particularly important to avoid voltages near these coercive points unless the ferroelectric capacitor is being accessed.
Referring to FIG. 3, there is illustrated a typical write sequence for a ferroelectric memory cell as in FIG. 1. Initially, the bitline (BL), wordline (WL), and plateline (PL) are all low. The upper row of hysteresis curves illustrates a write “1” and the lower row represents a write “0”. Either a “1” or “0” is initially stored in each exemplary memory cell. The write “1” is performed when the bitline BL and wordline WL are high and the plateline PL is low. This places a negative voltage across the ferroelectric capacitor and charges it to −Qs. When plateline PL goes high, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to −Qr. At the end of the write cycle, both bitline BL and plateline PL go low and stored charge −Qr remains on the ferroelectric capacitor. Alternatively, the write “0” occurs when bitline BL remains low and plateline PL goes high. This places a positive voltage across the ferroelectric capacitor and charges it to Qs representing a stored “0”. When plateline PL goes low, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to Qr representing a stored “0”.
A read operation is illustrated at FIG. 4 for the ferroelectric memory cell at FIG. 1. The upper row of hysteresis curves illustrates a read “0”. The lower row of hysteresis curves illustrates a read “1”. Wordline WL and plateline PL are initially low. Bitlines BL are precharged low. At time Δt0 bitline precharge signal PRE goes low, permitting the bitlines BL to float. At time Δt1 both wordline WL and plateline PL go high, thereby permitting each memory cell to share charge with a respective bitline. A stored “1” will share more charge with parasitic bitline capacitance CBL and produce a greater bitline voltage than the stored “0” as shown. A reference voltage (not shown) is produced at each complementary bitline of an accessed bitline. This reference voltage is between the “1” and “0” voltages. Sense amplifiers are activated at the time boundary between Δt1 and Δt2. When respective bitline voltages are fully amplified in time Δt2, the read “0” curve cell charge has increased from Qr to Qs. By way of comparison, the read “1” data state has changed from a stored “1” to a stored “0”. Thus, the read “0” operation is nondestructive, but the read “1” operation is destructive. At time Δt3, plateline PL goes low and applies −Vmax to the read “1” cell, thereby storing −Qs. At the same time, zero voltage is applied to the read “0” cell and charge Qr is restored. At the end of time Δt3, signal PRE goes high and precharges both bitlines BL to zero volts or ground. Thus, zero volts is applied to the read “1” cell and −Qr is restored.
The curves of FIG. 5 illustrate the effect of fatigue on a ferroelectric memory capacitor such as capacitor 100 of FIG. 1. The initial hysteresis curve is characteristic of a ferroelectric capacitor prior to fatigue. Repeated accesses to an individual ferroelectric capacitor cause a noticeable shift to hysteresis curve 502. The residual charge Qr, corresponding to a stored zero, has significantly degraded from point 504 to point 506. Likewise, the residual charge −Qr, corresponding to a stored one, has decreased from point 510 to point 508. The ferroelectric capacitor may be used in an individual memory cell or in a reference cell common to a column of memory cells. Thus, any shift of the hysteresis curve degrades the signal available for either a one or a zero. This degradation is particularly significant, however, for a reference cell which is accessed simultaneously with any other cell of the column.
Studies have shown a typical fatigue rate for ferroelectric capacitors on the order of 1012 cycles. By way of comparison, a typical electrically erasable programmable read only memory (EEPROM) will sustain 106 write and 1015 read cycles, respectively. Thus, a commercially feasible ferroelectric memory cell or reference cell should sustain at least 1014 read cycles. This is approximately two orders of magnitude greater than present ferroelectric capacitor fatigue rates.